A voltage comparator (hereinafter, simply a comparator) is used to compare two voltages to determine a magnitude relationship therebetween. FIG. 1 is a circuit diagram showing a configuration of an oscillator 10 using the comparator. The oscillator 10 includes a capacitor C1, a discharging switch SW1, a comparator 100r, a logic circuit 12, a current mirror circuit CM1, and a constant current source CS1.
One end of the capacitor C1 is grounded. The constant current source CS1 generates a predetermined reference current IREF. The current mirror circuit CM1 generates a charging current ICHG by multiplying the reference current IREF by a predetermined coefficient and supplies it to the capacitor C1. The discharging switch SW1 is provided in parallel with the capacitor C1.
The comparator 100r compares a ramp voltage VRAMP generated at the capacitor C1 and a predetermined peak voltage VPEAK to generate a comparative output CMP_OUT which is asserted (low level) when VRAMP>VPEAK. The logic circuit 12 generates a discharging signal CDIS which is asserted (high level) during a predetermined discharging period TDIS after the comparative output CMP_OUT is asserted, and outputs it to a control terminal (gate) of the discharging switch SW1 which is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
FIG. 2 shows waveform diagrams indicating operations of the oscillator 10 in FIG. 1, Prior to time t0, the discharging signal CDIS is asserted to turn on the discharging switch SW1. During this period, the ramp voltage VRAMP is 0 V. When the discharging signal CDIS is negated at time t0, the discharging switch SW1 is turned off, and the ramp voltage VRAMP increases with a constant gradient over time according to an equation (1).VRAMP=t×ICHG/C1  (1)
The discharging signal CDIS is asserted during the discharging period TDIS after the ramp voltage VRAMP reaches the peak voltage VPEAK at time t1, and negated again at time t2. The oscillator 10 repeats the operation performed during time t0 to time t2.
If the comparator 100r has an infinite response speed (i.e., zero delay), a cycle (TOSC) of the oscillator 10 is given by a sum of a slope period TSLOPE and the discharging period TDIS, as indicated in equations (2) and (3).TOSC=TSLOPE+TDIS  (2)TSLOPE=C1×VPEAK/ICHG  (3)
However, since the actual comparator 100r has a finite response speed, a delay τ occurs from when the VRAMP reaches the VPEAK until the comparative output CMP_OUT is asserted. In FIG. 2, waveforms when there is the delay τ are shown in broken lines. The delay τ is preferable to be as short as possible, since it affects the cycle of the oscillator 10.
Generally, it is necessary to increase an operating current (bias current) of the comparator 100r in order to accelerate its response speed. In particular, it is possible to reduce the delay τ by increasing a tail current of a differential amplifier provided on an initial stage or the bias current in an output stage of the comparator 100r. However, from a viewpoint of energy saving requirements for electronic apparatus in recent years, it is not preferable to conventionally increase the operating current of the comparator 100r. 